Transmitter Architectures
A transmitter is an output driver of an integrated circuit for the general purpose of transmitting signals originating from one device to other devices in an electronic system. In modern electronic systems, data transmission typically occurs at high data rates (>100 Mbps) over transmission-line type signal lines with transmitter and receiver end-terminations.
For long signal lines, it is common to employ differential signal encoding to mitigate the effects of signal degradation (e.g. noise), in addition to pre-emphasis techniques, the latter providing means for mitigating the effects of inter-symbol-interference caused by the transmission of data over a band-limited channel.
To generalize the utility of a transmitter circuit, the transmitter is often implemented with adjustable characteristics such as output amplitude, source terminations, and degree of pre-emphasis. In modern transmitter applications, data transmission efficiency is often achieved as part of a serialization/de-serialization (SERDES) link, in which parallel source data is serialized at a scaled data rate for transmission by a transmitter circuit over serial links, and subsequently received at a receiver circuit and de-serialized to recover the original parallel data.
Conventional Transmitter Architectures
Class A Transmitters
A class A transmitter structure typically consists of a single differential transistor pair with a tail current source and load resistors R driving a differential output voltage signal. TXOP-TXON, see FIG. 1A. INP and INN are respectively the positive and negative input portions of a differential input voltage signal INP-INN. Similarly, TXOP and TXON are the respective positive and negative transmit (TX) output portions of differential output voltage signal TXOP-TXON. Such a configuration is often referred to as a current-mode logic (CML) structure. “I” refers to the tail current source magnitude. The differential output voltage signal is shown being received by a floating termination load resistor RL, but could equivalently be a grounded and/or center-tapped termination.
Class AB Transmitters
A class AB transmitter structure typically consists of a parallel combination of pull-up and pull-down class A structures, with the differential transistor pair of each class A structure serving as the load resistors for the other class A structure, see FIG. 1B. A class AB structure is used for example in low voltage differential signaling (LVDS) applications. The differential output voltage signal TXOP-TXON is shown being received by a floating termination load resistor RL, but could equivalently be a grounded and/or center-tapped termination. In certain applications (not shown in FIG. 1B), the transmitter structure also includes an internal termination between TXOP and TXON.
Although not explicitly shown in FIG. 1B, a common-mode feedback (CMFB) is typically required via resistors RCMFB (large) and voltage signal VCMFB to achieve uniform head and tail current source magnitudes and a desired common-mode output level.
Voltage-Mode Transmitters
The class A and AB structures presented above have a basic commonality, in that the unit currents are directionally steered to generate a source current that ultimately produces a net voltage swing across a load resistance as an IR voltage drop. In this sense, they are inherently current-mode structures. A voltage-mode (VM) transmitter structure differs from these structures fundamentally in that, rather than generating a source current, it generates a source voltage, which subsequently produces a net voltage swing across a load resistance as a voltage division. Current state of the art for voltage mode transmitter architectures and related design methodologies are represented by the following public domain publications, which are incorporated herein by reference in their entirety: U.S. Pat. No. 6,448,813 to Garlepp, U.S. Pat. No. 6,812,733 to Plasterer U.S. Pat. No. 6,771,097 to Seng and Ho and U.S. Pat. No. 6,696,852 to Brunolli and Zhang, L.; Wilson, J.; Bashirullah, R.; Lei Luo; Jian Xu; Franzon, P, “Driver pre-emphasis techniques for on-chip global buses,” in Proc. 2005 Int. Symp. Low Power Electronics and Design, pp. 186-191.
An exemplary VM transmitter structure is illustrated in FIG. 2A. When the input is logically HIGH (INP HIGH and INN LOW), resistive paths are created between TXOP and VDD and between TXON and VSS. Similarly, when the input is logically LOW (INP LOW and INN HIGH), resistive paths are created between TXOP and VSS and between TXON and VDD. Any of the enabled resistive paths composed of R* and the effective drain-source resistance of the enabled transistor are generally balanced through transistor sizing, and may be denoted simply as “R”. That is, R is the sum of the physical resistor and the effective drain-source resistance of a MOS transistor. In practice, one would target an overall desired R, determine how it should be split up between fixed resistance (R*) and drain-source MOS resistance. Once that is determined, the MOS device simply needs to be sized properly to achieve the desired overall R. A preliminary MOS size can be worked out by hand and then tweaked in simulation. Together with an internal parallel termination resistor RT between TXOP and TXON, an unloaded voltage swing is determined as a voltage division of VDD-VSS by RT and 2 R. The loaded voltage swing is determined by another voltage division between the external load resistor RL and the output resistance of the transmitter.
An alternative but functionally equivalent version of the VM structure is illustrated in FIG. 2B, where the transistor pull-up and pull-down paths are encapsulated inside CMOS-like inverters and where only half as many R* resistors are needed. Again, the differential output voltage signal is shown being received by a floating termination load resistor RL, but could equivalently be a grounded and/or center-tapped termination, Further, it should be noted that the pull-up/pull-down structures presented in FIGS. 2A and 2B are analogous to the class AB current mode transmitter structure. VM structures analogous to class A current-mode structures may also be implemented.
Output Characteristics
The differential and common-mode output characteristics of the various transmitter structures presented thus far are summarized in Table 1. The ∥ notation is meant to convey “in parallel with”, as in conventional electronics nomenclature. ROdiff is the differential output resistance, VOdiff is the differential (loaded) output swing, RCM is the common-mode output impedance, and VCM is the common-mode output voltage.
TABLE 1Transmitter StructureParameterClass A1Class AB2,3VMROdiff2(R∥ro) ≈ 2R  2  ⁢      (                            R          CMFB                ⁢                                        r            o                    )                ⁢                                  ⁢                  (          large          )                ⁢                                  ⁢        2        ⁢                  (                                                    R                T                            2                        ⁢                                                        R                CMFB                                                    ⁢                          r              o                                )                    ≈              R        T            RT∥2R VOdiffI · (ROdiff∥RL)2 · I · (ROdiff∥RL)  2  ·  VDD  ·            R      T                      R        T            +              2        ⁢                                  ⁢        R              ·            R      L                      R        L            +              R                  O          diff                     RCM      1    2    ⁢      (          R      ⁢                                r          o                )                        r      o        4    ⁢          ⁢      (    large    )    R  2 VCM  VDD  -      R    ·          I      2      set by CMFB  VDD  2Notes:1For class A structures, ro represents the output resistance of the NMOS transistors2For class AB structures, ro represents the output resistance of either the PMOS or NMOS transistors. For simplicity, it is assumed that both device types have the same output resistance.3For class AB structures, the differential output impedance has two possible expressions. The first expression refers to the case of a transmitter without internal termination, and the second expression refers to the case for a transmitter with internal termination RT.For class AB structures, the large differential output impedance yields an approximate expression of 2·I·RL (or I·RL, for the case of an internally terminated transmitter with RT=RL) for the differential output swing. Further, in typical applications involving class A and VM structures, the differential output impedance of the transmitter is set to match the resistance of the termination—i.e. ROdiff=RL. For class A and VM structures, this yields
            I      ·                        R          L                2              ⁢                  ⁢    and    ⁢                  ⁢          VDD      ·                        R          T                                      R            T                    +                      2            ⁢            R                                ,respectively, for the differential voltage swing. It is further noted that, for the VM structure, the total resistance between VDD and VSS is 2 R+RT∥RL. Thus, one can write equivalent expressions for the supply current draw of each transmitter structure as a function of differential output voltage swing, as summarized in Table 2.
TABLE 2Transmitter StructureClass AClass AB1VM  I  =            2      ·              V                  O          diff                            R      L        I  ≈            V              O        diff                    2      ·              R        L              I  =            V              O        diff                            2        ·                  R          T                    ⁢                                R          L                       I  ≈            V              O        diff                    R      L      For class AB structures, the supply current draw has two possible expressions. The first expression refers to the case of a transmitter without internal termination, and the second expression refers to the case for a transmitter with internal termination RT=RL. As can be seen in Table 2, the class A transmitter structure consumes by far the most power for a given differential output swing, whereas the VM structure consumes the least.Challenges/Issues with Conventional ArchitecturesClass A and AB TransmittersHeadroom
For large output swing and/or low supply voltages, the settled headroom on the tail current sources in class A and AB transmitters is reduced, lowering its output impedance due to channel length modulation and providing less current to the output load than intended. It is common, for example in 0.13 μm designs with a 1.2V nominal supply voltage, to not be able to scale linearly the output swing beyond a certain point with a similar scaling of the nominal tail current source magnitude.
To get around this problem in class A designs, pull-up inductors on the transmitter outputs to VDD have been employed to bring up the common mode output level close to VDD, thus relieving headroom issues on the current source. The disadvantages of this approach are that on-chip inductors can be prohibitively large, and external inductors add to the bill of materials and can make board layout significantly more complicated. An alternative solution is to employ a higher-than-standard VDD supply on the output stage of the transmitter. One disadvantage of this approach is that reliability concerns are now present at the interface of the output stage and on the transistors in the output stage itself. Additionally, the need for an extra supply voltage can complicate on-chip power plane distribution and power net routing in the package. For class AB transmitters, this can complicate the interface with pre-driver circuitry.
Return Loss
For class A designs, as the output swing increases, the differential output impedance of the transmitter decreases with the degradation of the output resistance characteristics of the output stage differential pair. This in turn degrades the return loss of the transmitter. A class AB transmitter without internal termination has high output impedance and thus suffers from poor intrinsic return loss.
Common-Mode Level
For class A designs, the output common-mode level is typically referenced to a supply (VDD for a conventional NMOS-based design; VSS for a PMOS-based design) and varies (decreasing in the case of a conventional NMOS-based design) with increasing output swing. This can be problematic for applications in which there is a specification on the output common-mode level. A conventional class AB transmitter requires feedback control to establish the common-mode level. In some applications, a parallel combination of a class AB transmitter (without internal termination) with a VM transmitter has been used in place of common-mode feedback, see for example U.S. Pat. No. 6,812,733 to Plasterer et al. When this is done, it also addresses the problem of poor intrinsic return loss.
Interface with CMOS Pre-Drivers
In many transmitter designs, it is necessary to perform a number of processing and buffering operations (e.g. data serialization, data path multiplexing) in circuit stages prior to the transmitter output stage. The interface between these processing stages and the output stage is normally comprised of pre-driver buffer circuitry. If a conventional (NMOS-based design) class A or an AB transmitter output stage is directly interfaced to a pre-driver stage implemented as CMOS inverters, there is an inherent waste of a portion of the CMOS pre-driver output swing as the gates of the differential pair devices are driven below the gate-source voltage required to turn them off. Further, the ideal crossing level of the signal at the output of the CMOS pre-driver (from the perspective of the class A/AB output driver) will vary with output swing setting. Deviations from the ideal crossing level will result in unwanted duty-cycle distortion at the transmitter output.
VM Transmitters
The output characteristics of the conventional Voltage-Mode/Thevenin transmitter are dependent on resistors RT and R and are thus not adjustable. The interdependence of differential output impedance and output swing may make it difficult to meet potentially incompatible specifications for these parameters.
Common-Mode Adjustment
Some specifications require that the common-mode level be adjustable in a DC coupled environment. With the possible exception of the class AB transmitter, none of the conventional drivers presented in this section have a programmatic means to accomplish this. The class AB transmitter can potentially implement common-mode adjustment in the same manner (i.e. feedback) as it normally would.
Conventional Pre-Emphasis Implementations
For long signal lines, it is common to employ pre-emphasis techniques to mitigate the effects of inter-symbol-interference caused by the transmission of data over a band-limited channel. There are many different forms of pre-emphasis in transmitter implementations, see e.g. U.S. Pat. No. 6,680,681 and the references cited therein. Selected bits can either be emphasized or de-emphasized, and multiple emphasis methodologies can be employed simultaneously. The most common form is post-cursor pre-emphasis, in which “emphasized bits” immediately following a transition between output logic states have a larger magnitude than repeated bits at the same logic level. This form of pre-emphasis is illustrated in FIG. 3. In any of the conventional transmitter architectures, a typical implementation of pre-emphasis is achieved by splitting the output stage driver into separate drivers for regular drive and pre-emphasis drive (with shared termination resistors in the case of a class A transmitter). The regular drive portion of the output stage is operated with the normal input data, and the pre-emphasis portion is operated with a modified version of the input data (one-bit delayed and inverted in the case of post-cursor pre-emphasis).
Class A/AB Transmitter
A conventional pre-emphasis implementation involving a class A transmitter architecture is illustrated in FIG. 4. The arrangement would be completely analogous for class AB transmitters. The normal and pre-emphasis data inputs are SDP/SDN (serial data) and PSDP/PSDN (pre-emphasis serial data), respectively. In all figures herein, SDP and SDN refer respectively to the positive and negative portions of the serial data stream, which is the data intended to be transmitted. Similarly, PSDP and PSDN refer respectively the positive and negative portions of the pre-emphasis serial data stream. Generally, IREG>IPRE and I=IREG+IPRE. For the case of post-cursor pre-emphasis, when driving an emphasized bit, the two portions of the output stage driver operate constructively, providing a total current IREG+IPRE to produce the output swing. Similarly, when driving a non-emphasized bit, the two portions of the output stage driver operate destructively, providing a net current IREG−IPRE to produce the output swing. In either case, the total current drawn from VDD remains IREG+IPRE. Under these circumstances, the pre-emphasis ratio (PER—the ratio of non-emphasized to emphasized bit amplitude) can be derived from Table 1 by substituting for I:
                    PER        =                                            I              REG                        -                          I              PRE                                                          I              REG                        +                          I              PRE                                                          (        1        )            VM Transmitter
A conventional pre-emphasis implementation involving a VM transmitter architecture is illustrated in FIG. 5. For post-cursor pre-emphasis, PSDP/PSDN is a one-bit delayed and inverted version of SDP/SDN. RREG* and RPRE* are analogous to R* from various other figures—i.e. they are physical resistors. The subscript suffixes merely differentiate between the regular and pre-emphasis paths of the transmitter. The two portions of the output stage driver are differentiated by the magnitude of the resistive path established between the transmitter outputs and the supply. In the case of the regular drive portion, resistive paths of RREG are established (RREG*+the transistor drain-source resistance). For the pre-emphasis drive portion, resistive paths of RPRE are established. Generally, RPRE>RREG and, R is the parallel combination of RREG and RPRE. For the case of post-cursor pre-emphasis, when driving an emphasized bit, the two portions of the output stage driver operate constructively to establish the output swing. Similarly, when driving a non-emphasized bit, the two portions of the output stage driver operate destructively to establish the output swing.
FIG. 6A shows the equivalent resistive paths for the VM transmitter configured to drive an emphasized bit with SDP and PSDP both HIGH. Output characteristics in this configuration are readily obtained from Table 1. FIG. 6B shows equivalent resistive paths for the VM transmitter configured to drive a non-emphasized bit with SDP HIGH and PSDP LOW. In FIG. 6, RREG and RPRE are analogous to the composite R discussed in the section on Voltage Mode transmitters earlier in this disclosure. It comprises the physical resistor RREG* or RPRE*, plus the effective drain-source resistance of the enabled MOS device (which depends on what the data is, of course) in the inverters depicted in FIG. 5.
The output characteristics of a VM transmitter driving a non-emphasized bit are given in Equation 2.
                                          R                          O              diff                                =                                    R              T                        ⁢                                                        2                ⁢                                  (                                      R                    REG                                                                    ⁢                                  R                  PRE                                            )                                      ⁢                                  ⁢                              V                          O              diff                                =                      2            ·            VDD            ·                          (                                                1                                      R                    REG                                                  -                                  1                                      R                    PRE                                                              )                        ·                                          R                                  O                  diff                                            2                        ·                                          R                L                                                              R                  L                                +                                  R                                      O                    diff                                                                                                          (        2        )            The PER for a VM transmitter then becomes:
                    PER        =                                            R              PRE                        -                          R              REG                                                          R              PRE                        +                          R              REG                                                          (        3        )            Supply Current Draw
One consequence of implementing conventional pre-emphasis for a VM transmitter is that the current draw from VDD is dependent on whether the bit being transmitted is emphasized or not. This can be detailed in terms of the equivalent resistance between VDD and VSS depending on whether the current bit is emphasized or non-emphasized. Equation 4 gives the VDD/VSS resistance for a VM transmitter with pre-emphasis
                                          R            E                    =                      2            ⁢                          (                                                                    R                    REG                                    ⁢                                                                                R                      PRE                                        )                                                  +                                  R                  T                                                                    ⁢                          R              L                        ⁢                                                  ⁢                          (              emphasized              )                                      ⁢                                  ⁢                                                                              R                  NE                                =                                                                            2                      ⁢                                              (                                                                              R                            REG                                                    ⁢                                                                                                                                      ⁢                                                      R                            PRE                                                                          )                                                              +                                                                  R                        T                                            ⁢                                                                                                                  ⁢                                              R                        L                                                                                                  [                                          1                      +                                                                        2                          ⁢                                                      (                                                                                          R                                T                                                            ⁢                                                                                                                                                          ⁢                                                              R                                L                                                                                      )                                                                                                                                R                            REG                                                    +                                                      R                            PRE                                                                                                                ]                                                                                                                          =                                                                            R                      E                                                              [                                              1                        +                                                                              2                            ⁢                                                          (                                                                                                R                                  T                                                                ⁢                                                                                                                                                                    ⁢                                                                  R                                  L                                                                                            )                                                                                                                                          R                              REG                                                        +                                                          R                              PRE                                                                                                                          ]                                                        ⁢                                                                          ⁢                                      (                                          non                      ⁢                                              -                                            ⁢                      emphasized                                        )                                                                                      ⁢                                  ⁢                                                                                                  R                    E                                                        R                    NE                                                  =                                  1                  +                                                            2                      ⁢                                              (                                                                              R                            T                                                    ⁢                                                                                                                                      ⁢                                                      R                            L                                                                          )                                                                                                            R                        REG                                            +                                              R                        PRE                                                                                                                                                                    =                                  1                  +                                                            2                      ⁢                                              (                                                                              R                            T                                                    ⁢                                                                                                                                      ⁢                                                      R                            L                                                                          )                                            ⁢                                              (                                                  1                          -                          PER                                                )                                                                                    2                      ⁢                                              R                        REG                                                                                                                                                    (        4        )            Equation shows that more power is dissipated when driving a non-emphasized bit (RNE is always smaller than RE) and that the fraction by which this power exceeds that of driving an emphasized bit increases with decreasing PER (i.e. with more pre-emphasis). A pattern-dependent supply current draw (beyond any current spikes occurring during transitions) is generally an undesirable feature of a transmitter.
In summary, prior art voltage mode transmitter structures have been implemented with a fixed configuration, resulting in fixed characteristics for a given load such as a fixed differential output voltage swing, fixed differential and common-mode output impedance and fixed common-mode output level. Further, the implementation of pre-emphasis for voltage-mode structures in an analogous manner to current-mode transmitter structures results in undesirable characteristics such as data-dependent power dissipation. Consequently, there is a need for, and it would be advantageous to have a voltage mode transmitter structure that addresses these limitations.